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1. general description the 74HC73 is a high-speed si-gate cmos device and is pin compatible with low-power schottky ttl (lsttl). the 74HC73 is speci?ed in compliance with jedec standard no. 7a. the 74hc is a dual negative-edge triggered jk ?ip-?op featuring individual j, k, clock (n cp) and reset (n r) inputs; also complementary nq and n q outputs. the j and k inputs must be stable one set-up time prior to the high-to-low clock transition for predictable operation. the reset (n r) is an asynchronous active low input. when low, it overrides the clock and data inputs, forcing the nq output low and the n q output high. schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. features n low-power dissipation n complies with jedec standard no. 7a n esd protection: u hbm eia/jesd22-a114-b exceeds 2000 v u mm eia/jesd22-a115-a exceeds 200 v. n multiple package options n speci?ed from - 40 cto+80 c and from - 40 c to +125 c. 74HC73 dual jk ?ip-?op with reset; negative-edge trigger rev. 03 12 november 2004 product data sheet
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 2 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger 3. quick reference data [1] c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ ? (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l v cc 2 f o ) = sum of outputs. 4. ordering information table 1: quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns. symbol parameter conditions min typ max unit t phl , t plh propagation delay c l = 15 pf; v cc =5 v - - n cp to nq - 16 - ns n cp to n q - 16 - ns n r to nq, n q - 15 - ns f max maximum clock frequency c l = 15 pf; v cc = 5 v - 77 - mhz c i input capacitance - 3.5 - pf c pd power dissipation capacitance per ?ip-?op v i = gnd to v cc [1] -30-pf table 2: ordering information type number package temperature range name description version 74HC73n - 40 c to +125 c dip14 plastic dual in-line package; 14 leads (300 mil) sot27-1 74HC73d - 40 c to +125 c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74HC73db - 40 c to +125 c ssop14 plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 74HC73pw - 40 c to +125 c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 3 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger 5. functional diagram fig 1. functional diagram fig 2. logic symbol fig 3. iec logic symbol 001aab981 q 1q 12 1j 14 q r 1q 13 j 1cp 1 1k 3 1r 2 cp ff1 k q 2q 9 2j 7 q r 2q 8 j 2cp 5 2k 10 2r 6 cp ff2 k 001aab979 q 1q 12 2q 9 1j 14 2j 7 q r 1q 13 2q 8 j 1cp 1 2cp 5 1k 3 2k 1r 2r 26 10 cp ff k 001aab980 13 12 1j 1k 3 r 2 1 4 c1 8 9 1j 1k 10 r 6 5 7 c1
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 4 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger 6. pinning information 6.1 pinning 6.2 pin description fig 4. logic diagram (one ?ip-?op) 001aab982 c c k j r cp c c c c c c c c q q fig 5. pin con?guration 73 1cp 1j 1r 1q 1k 1q v cc gnd 2cp 2k 2r 2q 2j 2q 001aab978 1 2 3 4 5 6 7 8 10 9 12 11 14 13 table 3: pin description symbol pin description 1 cp 1 clock input for ?ip-?op 1 (high-to-low, edge-triggered) 1 r 2 asynchronous reset input for ?ip-?op 1 (active low) 1k 3 synchronous k input for ?ip-?op 1 v cc 4 positive supply voltage 2 cp 5 clock input for ?ip-?op 2 (high-to-low, edge-triggered) 2 r 6 asynchronous reset input for ?ip-?op 2 (active low) 2j 7 synchronous j input for ?ip-?op 2 2 q 8 complement ?ip-?op 2 output 2q 9 true ?ip-?op 2 output 2k 10 synchronous k input for ?ip-?op 2
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 5 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger 7. functional description 7.1 function table [1] h = high voltage level; h = high voltage level one set-up time prior to the high-to-low cp transition; l = low voltage level; i = low voltage level one set-up time prior to the high-to-low cp transition; q = state of referenced output one set-up time prior to the high-to-low cp transition; x = dont care; = high-to-low cp transition. 8. limiting values [1] above 70 c: p tot derates linearly with 12 mw/k. [2] above 70 c: p tot derates linearly with 8 mw/k. gnd 11 ground (0 v) 1q 12 true ?ip-?op 1 output 1 q 13 complement ?ip-?op 1 output 1j 14 synchronous j input for ?ip-?op 1 table 3: pin description continued symbol pin description table 4: function table [1] input output operating mode n r n cp nj nk nq n q l x x x l h asynchronous reset h hh q q toggle l h l h load 0 (reset) h l h l load 1 (set) llq q hold (no change) table 5: limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +7 v i ik input diode current v i < - 0.5 v or v i >v cc + 0.5 v - 20 ma i ok output diode current v o < - 0.5 v or v o >v cc + 0.5 v - 20 ma i o output source or sink current v o = - 0.5 v to v cc + 0.5 v - 25 ma i cc , i gnd v cc or gnd current - 50 ma t stg storage temperature - 65 +150 c p tot power dissipation dip14 package [1] - 750 mw so14, ssop14 and tssop14 packages [2] - 500 mw
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 6 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger 9. recommended operating conditions 10. static characteristics table 6: recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 2.0 5.0 6.0 v v i input voltage 0 - v cc v v o output voltage 0 - v cc v t r , t f input rise and fall times except for n cp v cc = 2.0 v - - 1000 ns v cc = 4.5 v - 6.0 500 ns v cc = 6.0 v - - 400 ns t amb ambient temperature - 40 - +125 c table 7: static characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit t amb =25 c v ih high-level input voltage v cc = 2.0 v 1.5 1.2 - v v cc = 4.5 v 3.15 2.4 - v v cc = 6.0 v 4.2 3.2 - v v il low-level input voltage v cc = 2.0 v - 0.8 0.5 v v cc = 4.5 v - 2.1 1.35 v v cc = 6.0 v - 2.8 1.8 v v oh high-level output voltage v i =v ih or v il i o = - 20 m a; v cc = 2.0 v 1.9 2.0 - v i o = - 20 m a; v cc = 4.5 v 4.4 4.5 - v i o = - 20 m a; v cc = 6.0 v 5.9 6.0 - v i o = - 4 ma; v cc = 4.5 v 3.98 4.32 - v i o = - 5.2 ma; v cc = 6.0 v 5.48 5.81 - v v ol low-level output voltage v i =v ih or v il i o =20 m a; v cc = 2.0 v - 0 0.1 v i o =20 m a; v cc = 4.5 v - 0 0.1 v i o =20 m a; v cc = 6.0 v - 0 0.1 v i o = 4 ma; v cc = 4.5 v - 0.15 0.26 v i o = 5.2 ma; v cc = 6.0 v - 0.16 0.26 v i li input leakage current v i =v cc or gnd; v cc = 6.0 v - - 0.1 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 a; v cc = 6.0 v - - 4.0 m a c i input capacitance - 3.5 - pf
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 7 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger t amb = - 40 c to +85 c v ih high-level input voltage v cc = 2.0 v 1.5 - - v v cc = 4.5 v 3.15 - - v v cc = 6.0 v 4.2 - - v v il low-level input voltage v cc = 2.0 v - - 0.5 v v cc = 4.5 v - - 1.35 v v cc = 6.0 v - - 1.8 v v oh high-level output voltage v i =v ih or v il i o = - 20 m a; v cc = 2.0 v 1.9 - - v i o = - 20 m a; v cc = 4.5 v 4.4 - - v i o = - 20 m a; v cc = 6.0 v 5.9 - - v i o = - 4 ma; v cc = 4.5 v 3.84 - - v i o = - 5.2 ma; v cc = 6.0 v 5.34 - - v v ol low-level output voltage v i =v ih or v il i o =20 m a; v cc = 2.0 v - - 0.1 v i o =20 m a; v cc = 4.5 v - - 0.1 v i o =20 m a; v cc = 6.0 v - - 0.1 v i o = 4 ma; v cc = 4.5 v - - 0.33 v i o = 5.2 ma; v cc = 6.0 v - - 0.33 v i li input leakage current v i =v cc or gnd; v cc = 6.0 v - - 1.0 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 a; v cc = 6.0 v - - 40.0 m a table 7: static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 8 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger t amb = - 40 c to +125 c v ih high-level input voltage v cc = 2.0 v 1.5 - - v v cc = 4.5 v 3.15 - - v v cc = 6.0 v 4.2 - - v v il low-level input voltage v cc = 2.0 v - - 0.5 v v cc = 4.5 v - - 1.35 v v cc = 6.0 v - - 1.8 v v oh high-level output voltage v i =v ih or v il i o = - 20 m a; v cc = 2.0 v 1.9 - - v i o = - 20 m a; v cc = 4.5 v 4.4 - - v i o = - 20 m a; v cc = 6.0 v 5.9 - - v i o = - 4 ma; v cc = 4.5 v 3.7 - - v i o = - 5.2 ma; v cc = 6.0 v 5.2 - - v v ol low-level output voltage v i =v ih or v il i o =20 m a; v cc = 2.0 v - - 0.1 v i o =20 m a; v cc = 4.5 v - - 0.1 v i o =20 m a; v cc = 6.0 v - - 0.1 v i o = 4 ma; v cc = 4.5 v - - 0.4 v i o = 5.2 ma; v cc = 6.0 v - - 0.4 v i li input leakage current v i =v cc or gnd; v cc = 6.0 v - - 1.0 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 a; v cc = 6.0 v - - 80.0 m a table 7: static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 9 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger 11. dynamic characteristics table 8: dynamic characteristics gnd = 0 v; t r =t f = 6 ns; c l = 50 pf; see figure 8 . symbol parameter conditions min typ max unit t amb = 25 c t phl , t plh propagation delay n cp to nq see figure 6 v cc = 2.0 v - 52 160 ns v cc = 4.5 v - 19 32 ns v cc = 6.0 v - 15 27 ns v cc = 5.0 v; c l =15pf - 16 - ns propagation delay n cp to n q see figure 6 v cc = 2.0 v - 52 160 ns v cc = 4.5 v - 19 32 ns v cc = 6.0 v - 15 27 ns v cc = 5.0 v; c l =15pf - 16 - ns propagation delay n r to nq, n q see figure 7 v cc = 2.0 v - 50 145 ns v cc = 4.5 v - 18 29 ns v cc = 6.0 v - 14 25 ns v cc = 5.0 v; c l =15pf - 15 - ns t thl , t tlh output transition time see figure 6 v cc = 2.0 v - 19 75 ns v cc = 4.5 v - 7 15 ns v cc = 6.0 v - 6 13 ns t w n cp clock pulse width high or low see figure 6 v cc = 2.0 v 80 22 - ns v cc = 4.5 v 16 8 - ns v cc = 6.0 v 14 6 - ns n r reset pulse width high or low see figure 7 v cc = 2.0 v 80 22 - ns v cc = 4.5 v 16 8 - ns v cc = 6.0 v 14 6 - ns t rem removal time n r to n cp see figure 7 v cc = 2.0 v 80 22 - ns v cc = 4.5 v 16 8 - ns v cc = 6.0 v 14 6 - ns t su set-up time nj, nk to n cp see figure 6 v cc = 2.0 v 80 22 - ns v cc = 4.5 v 16 8 - ns v cc = 6.0 v 14 6 - ns
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 10 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger t h hold time nj, nk to n cp see figure 6 v cc = 2.0 v 3 - 8- ns v cc = 4.5 v 3 - 3- ns v cc = 6.0 v 3 - 2- ns f max maximum clock frequency see figure 6 v cc = 2.0 v 6.0 23 - mhz v cc = 4.5 v 30 70 - mhz v cc = 6.0 v 35 83 - mhz v cc = 5.0 v; c l = 15 pf - 77 - mhz c pd power dissipation capacitance per ?ip-?op v i = gnd to v cc [1] -30-pf t amb = - 40 c to +85 c t phl , t plh propagation delay n cp to nq see figure 6 v cc = 2.0 v - - 200 ns v cc = 4.5 v - - 40 ns v cc = 6.0 v - - 34 ns propagation delay n cp to n q see figure 6 v cc = 2.0 v - - 200 ns v cc = 4.5 v - - 40 ns v cc = 6.0 v - - 34 ns propagation delay n r to nq, n q see figure 7 v cc = 2.0 v - - 180 ns v cc = 4.5 v - - 36 ns v cc = 6.0 v - - 31 ns t thl , t tlh output transition time see figure 6 v cc = 2.0 v - - 95 ns v cc = 4.5 v - - 19 ns v cc = 6.0 v - - 16 ns t w n cp clock pulse width high or low see figure 6 v cc = 2.0 v 100 - - ns v cc = 4.5 v 20 - - ns v cc = 6.0 v 17 - - ns n r reset pulse width high or low see figure 7 v cc = 2.0 v 100 - - ns v cc = 4.5 v 20 - - ns v cc = 6.0 v 17 - - ns t rem removal time n r to n cp see figure 7 v cc = 2.0 v 100 - - ns v cc = 4.5 v 20 - - ns v cc = 6.0 v 17 - - ns table 8: dynamic characteristics continued gnd = 0 v; t r =t f = 6 ns; c l = 50 pf; see figure 8 . symbol parameter conditions min typ max unit
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 11 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger t su set-up time nj, nk to n cp see figure 6 v cc = 2.0 v 100 - - ns v cc = 4.5 v 20 - - ns v cc = 6.0 v 17 - - ns t h hold time nj, nk to n cp see figure 6 v cc = 2.0 v 3 - - ns v cc = 4.5 v 3 - - ns v cc = 6.0 v 3 - - ns f max maximum clock frequency see figure 6 v cc = 2.0 v 4.8 - - mhz v cc = 4.5 v 24 - - mhz v cc = 6.0 v 28 - - mhz t amb = - 40 c to +125 c t phl , t plh propagation delay n cp to nq see figure 6 v cc = 2.0 v - - 240 ns v cc = 4.5 v - - 48 ns v cc = 6.0 v - - 41 ns propagation delay n cp to n q see figure 6 v cc = 2.0 v - - 240 ns v cc = 4.5 v - - 48 ns v cc = 6.0 v - - 41 ns propagation delay n r to nq, n q see figure 7 v cc = 2.0 v - - 220 ns v cc = 4.5 v - - 44 ns v cc = 6.0 v - - 38 ns t thl , t tlh output transition time see figure 6 v cc = 2.0 v - - 110 ns v cc = 4.5 v - - 22 ns v cc = 6.0 v - - 19 ns t w n cp clock pulse width high or low see figure 6 v cc = 2.0 v 120 - - ns v cc = 4.5 v 24 - - ns v cc = 6.0 v 20 - - ns n r reset pulse width high or low see figure 7 v cc = 2.0 v 120 - - ns v cc = 4.5 v 24 - - ns v cc = 6.0 v 20 - - ns table 8: dynamic characteristics continued gnd = 0 v; t r =t f = 6 ns; c l = 50 pf; see figure 8 . symbol parameter conditions min typ max unit
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 12 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger [1] c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ ? (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l v cc 2 f o ) = sum of outputs. t rem removal time n r to n cp see figure 7 v cc = 2.0 v 120 - - ns v cc = 4.5 v 24 - - ns v cc = 6.0 v 20 - - ns t su set-up time nj, nk to n cp see figure 6 v cc = 2.0 v 120 - - ns v cc = 4.5 v 24 - - ns v cc = 6.0 v 20 - - ns t h hold time nj, nk to n cp see figure 6 v cc = 2.0 v 3 - - ns v cc = 4.5 v 3 - - ns v cc = 6.0 v 3 - - ns f max maximum clock frequency see figure 6 v cc = 2.0 v 4.0 - - mhz v cc = 4.5 v 20 - - mhz v cc = 6.0 v 24 - - mhz table 8: dynamic characteristics continued gnd = 0 v; t r =t f = 6 ns; c l = 50 pf; see figure 8 . symbol parameter conditions min typ max unit
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 13 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger 12. waveforms the shaded areas indicate when the input is permitted to change for predictable output performance. v m = 0.5 v i . fig 6. waveforms showing the clock (n cp) to output (nq, n q) propagation delays, the clock pulse width, the j and k to n cp set-up and hold times, the output transition times and the maximum clock frequency v m = 0.5 v i . fig 7. waveforms showing the reset (n r) input to output (nq, n q) propagation delays and the reset pulse width and the n r to n cp removal time t su 1/f max t h ncp input v m v m t h t su t w nj, nk input 001aab983 nq output nq output t phl t plh v m t tlh t thl t tlh v m t thl t plh t phl 001aab984 nq output t w nr input v m nq input ncp input v m t rem t phl t plh
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 14 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger test data is given in t ab le 9 . de?nitions for test circuit: r t = termination resistance should be equal to output impedance z o of the pulse generator. c l = load capacitance including jig and probe capacitance. fig 8. load circuitry for switching times table 9: test data supply input load v cc v i t r , t f c l 2.0 v v cc 6 ns 50 pf 4.5 v v cc 6 ns 50 pf 6.0 v v cc 6 ns 50 pf 5.0 v v cc 6 ns 15 pf mna101 v cc v i v o r t c l pulse generator d.u.t.
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 15 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger 13. package outline fig 9. package outline sot27-1 (dip14) unit a max. 1 2 (1) (1) b 1 cd (1) z ee m h l references outline version european projection issue date iec jedec jeita mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot27-1 99-12-27 03-02-13 a min. a max. b max. w m e e 1 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 2.2 4.2 0.51 3.2 0.068 0.044 0.021 0.015 0.77 0.73 0.014 0.009 0.26 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.087 0.17 0.02 0.13 050g04 mo-001 sc-501-14 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 14 1 8 7 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. dip14: plastic dual in-line package; 14 leads (300 mil) sot27-1
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 16 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger fig 10. package outline sot108-1 (so14) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 17 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger fig 11. package outline sot337-1 (ssop14) unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 0.2 7.9 7.6 1.03 0.63 0.9 0.7 1.4 0.9 8 0 o o 0.13 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot337-1 99-12-27 03-02-19 (1) w m b p d h e e z e c v m a x a y 1 7 14 8 q a a 1 a 2 l p q detail x l (a ) 3 mo-150 pin 1 index 0 2.5 5 mm scale ssop14: plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 a max. 2
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 18 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger fig 12. package outline sot402-1 (tssop14) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index
9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 19 of 21 philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger 14. revision history table 10: revision history document id release date data sheet status change notice doc. number supersedes 74HC73_3 20041112 product data sheet - 9397 750 13815 74hc_hct73_cnv_2 modi?cations: ? the format of this data sheet has been redesigned to comply with the current presentation and information standard of philips semiconductors. ? removed type number 74hct73. ? inserted family speci?cation. 74hc_hct73_cnv_2 19970911 product speci?cation - - 74hc_hct73_1 74hc_hct73_1 19901201 product speci?cation - - -
philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger 9397 750 13815 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data sheet rev. 03 12 november 2004 20 of 21 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 18. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 12 november 2004 document number: 9397 750 13815 published in the netherlands philips semiconductors 74HC73 dual jk ?ip-?op with reset; negative-edge trigger 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 recommended operating conditions. . . . . . . . 6 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 9 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 15 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20 16 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 18 contact information . . . . . . . . . . . . . . . . . . . . 20

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